In the previous installment of the series we’ve gone through the high-level design decisions that you have to make when designing an H-Bridge, and we’ve discussed the considerations for selecting the MOSFETs and the catch diodes that will make up the bridge.
In this article I will go through the available options for drive circuits. We will discuss the trade-offs between them and what influences the various parameters of the drive circuits.
You will take the most out of this write-up if you are already fairly familiar with H-Bridge basics, so if you aren’t, I suggest you read the introductory piece of the series first. Understanding of the various drive-modes will also be useful, so reading the sign-magnitude drive, the lock anti-phase drive and the asynchronous sign-magnitude drive articles isn’t a waste of time either, though those pieces go into quite a bit of more detail than what is needed to follow this text.
To make referencing easier, let’s review the H-Bridge circuit:
and our motor model:
The drive circuitry for an H-Bridge is basically the electronics that sits between the PWM (and potentially other) digital control inputs and the MOSFET gates. It has two major purposes:
- Translate the input voltages to suitable levels to drive the gates
- Provide enough current to charge and discharge the gates fast enough
On top of that, many drive circuits include additional functionality:
- Translate the input command into gate-drive signals according to the drive mode
- Provide shoot-through protection
- Generate voltages for the high-side gate-drive circuitry (for N-channel drivers)
- Provide additional safety functions, like over-current protection
- Control the turn-on and turn-off times of the FETs
Drive circuits can come in many shape or form.
- There are low-side drivers, that are designed to drive Q2 or Q4 on our bridge.
- High-side drivers in turn are designed to drive Q1 or Q3.
- Half-bridge drivers combine one low- and one high-side driver, so they can drive Q1 and Q2 (or Q3 and Q4) together.
- Full-bridge drivers obviously have two low-side and two high-side drivers so they can drive all four FETs.
As we’ve discussed in the previous article, low-side MOSFETs are always N-channel ones, while on the high-side we can you either P-channel or N-channel devices. This means that when we discuss high-side drivers (or half- and full-bridge drivers) we have to create two sub-categories, one for each channel-type.
Before we dive into the details, let’s get familiar with the mother of all driver circuits, the complementer CMOS driver:
In this circuit, a high-side PMOS and a low-side CMOS FET are combined to provide a clean digital logic output: if the input (the gates of the FETs) is grounded, the low-side FET is off, while the high-side is on. The output is connected to Vcc through the relatively low rrdson_high of the high-side element. When the input is connected to Vcc, the opposite happens, and the low-side FET starts conducting, while the high-side FET is off, so the output is connected to ground through a similarly low rdson_low. This topology is fairly common amongst not just bridge drivers, but logic gates and in general digital logic. We will use it as our starting example, and expand to more complicated circuits as we discuss the problems that come up.
In case you were wondering how is this driver stage different from one side of an H-bridge:
- The FETs are much smaller, so their gate capacitance is really small. Even a relatively weak source can quickly charge and dis-charge them.
- These smaller FETs also have a much higher rdson value (several ohms) so the dynamic shoot-through currents are low enough not be a headache.
This drive stage will be the building block for all of our low- and high-side drivers, but with some modifications on occasion. I’ll start with low-side drivers and discuss the problems you will face with them. Some of the discussion will be applicable (with slight changes) to high-side drivers. After those topics are cleared, we can continue on to high-side drivers.
As I have said, this drive configuration is the same that is used in CMOS digital logic. (TTL and some other logic technologies are significantly different!) Because of this, as a concrete example, I’ll use the output stage of the AHC logic series to discuss the features and characteristics of this type of driver.
Calculating turn-on and off times
As we’ve discussed it in the previous part of the series, the gate capacitance of the MOSFETs together with the available drive current from the drive circuit will determine how fast the transistor can be turned on or off. Let’s investigate that topic a little more in detail!
In the following I will only concentrate on a low-side, N-channel device and it’s driver. You can easily convert the results to a high-side drive situation for both the N- and P-channel cases.
FET datasheets specify the gate capacitance, sometime called the input capacitance. The capacitance varies a lot depending on the size of the device. For example, this relatively large MOSFET (the PHK31NQ03LT from NXP) has an almost 5nF gate capacitance. At the same time this transistor has a less than 5mΩ on-resistance. Another example would be IXTY 01N80. This 50mΩ on-resistance transistor only has a roughly 60pF gate capacitance. The FETs used in my Servo Brain µModule project have a roughly 100mΩ rdson and a roughly 350pF gate capacitance.
To calculate the turn-on and off times we need to know a couple of things: how high the gate-voltage needs to be and how fast the drive circuitry can charge and discharge the gate-capacitance. Let’s address these questions in order: the minimum gate-voltage that is needed to turn the FET fully on is specified in the datasheet, but also depends on the drain current. It is usually specified in the form of a chart like this (this is from Wikipedia):
As you can see, for relatively low drain-currents (Y axis) the FET operates as a small resistance (the curve is linear and goes through the origin). For high currents however, the FET transitions into so-called saturation where the current is pretty much constant. For our application, we want to keep the FET in it’s linear (resistor-like) region. So, if you know the maximum current the FET (which is the current limit of the bridge), you can figure out the minimum gate-voltage that is needed to keep the FET linear. To take a practical example, let’s use the FDMS8880 FET and lets assume we want to build a bridge with a 20A current limit. The same diagram for this particular FET looks like this
You see that if the gate voltage (Vgs) is only three volts, the FET would not even be able to conduct 20A. It saturates at around 15A. With a gate voltage of 3.5V, you can get the device back into it’s linear region for 20A current, but it’s resistance is still a bit high. If you however increase the gate voltage to about 4.5V, you’ll see that the resistance at 20A does not depend on the gate voltage too much any more. So, for our case, we would need a gate voltage of at least 4.5V.
In order to turn the same FET off, we need to lower the gate voltage below the so-called threshold voltage. This is again something that’s specified in the datasheet, for this particular device, it’s 1.2V (minimum).
Now, on to the second question: how fast can the driver charge or dis-charge the gate of the MOSFET. Driver characteristics are usually quite complex, and they are specified using charts, like this:
Here you see how the output current changes as the function of the output voltage, or the more useful way of looking at it: if you want to draw a certain amount of current out of the pin, how much the output voltage will deviate from its ideal value. This particular chart is from TI and specifies their AHC-series logic output characteristics (page 16). Notice how these charts are fairly similar to the charts above for MOSFET characteristics. This is not a coincidence, as the AHC series uses our complementer FET output drive circuit.
To approximate these curves, we can use a very simple model (again, using the MOSFET terminology): The output is in saturation mode for high currents – effectively acting as a current-source – and as the current decreases, it transitions into a linear region where it acts as a resistor. Graphically, we approximate the curve with two lines:
You can easily see that for the case of driving high voltages, the current source is at around 17mA, and the resistance is around 100Ω. When the output drives low, it can output 21mA and has roughly 70Ω resistance. (It is typical that an output stage has a somewhat weaker high-side driver, being a P-MOS device.)
In many cases you can even further simplify the picture and assume either only the current-source or the linear region. We will go though all three approaches, using an example: as we’ve seen before, the FDMS8880 MOSFET can be turned on completely by a 4.5 or greater gate voltage. So, in theory it can be driven directly by a 5V digital pin. Let’s say we use the previously studied AHC-series to drive the gate of this transistor.
Constant current drivers
The constant current approach works the following way: we try to charge up a capacitor with a constant current source to (at least) a certain voltage. That will take some time:
ton = Vgate*Cgate/Isource, where Vgate is the gate voltage we need to turn the FET completely on, Cgate is the gate capacitance, and Isource is the current the driver can source.
The off-time could be calculated like this:
toff = (Vgate-Vth)*Cgate/Isink, where Vth is the threshold voltage.
Substituting the numbers for out example we get the following:
ton = 4.5V*1585pF/17mA = 419ns
toff = (4.5V-1.2V)*1585pF/21mA = 249ns
Constant resistor drivers
The constant resistor approximation is more complex, because of the exponential response of the RC circuit. The turn-on time will be the following:
ton = –Rsource*Cgate * ln(1-Vgate/Vsource), where Rsource is the source resistance and Vsource is the high-level no-load voltage of the driver.
Similarly the off-time can be calculated as follows:
toff = –Rsink*Cgate * ln(Vth/Vsource)
To be able to use this model for anything meaningful, we will have to assume that Vgate is lower than Vsource, in other words, the FET is fully on with a gate voltage that’s less the drivers no-load output voltage.
Doing the calculations for our example we get:
ton = –100Ω*1585pF * ln(1-4.5V/5V) = 364ns
toff = –70Ω*1585pF * ln(1.2V/5V) = 158ns
You can see that there’s quite a difference between the two estimations. Both are actually under-estimating the times: the constant current approach will assume more current than the driver can actually deliver at low output voltage drops, while the constant resistance approach (at least the way I did it here) over-estimates the current for the saturated region.
Piece-wise linear model
A more precise estimate can be made by combining the two methods, and assume constant current charge and discharge until the knee-point (2.9V and 1.4V respectively for our example) and assume constant resistance only for the remaining portion:
ton = Vknee_on*Cgate/Isource – Rsource*Cgate * ln(1-(Vgate-Vknee_on)/(Vsource-Vknee_on))
toff = (Vsource-Vknee_off)*Cgate/Isink – Rsink*Cgate * ln(Vth/Vknee)
With this approach, we get:
ton = 497ns
toff = 286ns
These calculations can be done for P-channel MOSFETs and drivers as well, but of course you have to slightly change the equations to accommodate for the negative gate-source voltage of those devices.
Controlling turn-on and off times
So far so good, we have several ways now to calculate the transient times, with various accuracy. But what if you’re not satisfied with the results? What tools do you have to influence these numbers?
If you want to make the time shorter, your pretty much have two choices: either change the FET to one with a lower gate capacitance or you change the driver to one that can provide more current.
If you want to make the time longer, you have more options. One thing you can do is to add more capacitance to the gate by adding an extra capacitor towards ground for example.
By far the most common way of controlling the trun-on and –off times is to add a series resistor to the driver outputs:
The series resistor method is ineffective if the driver is truly a current source, but that very rarely is the case. Normally, the effect is two-fold: one is that (by requiring more voltage for the same current) it gets the driver faster out of its current source region into it linear region. The second affect is that, once we’re in the linear region, the effective source resistance of the driver will be higher, so the time-constant of the charge-up or down of the capacitor will be larger.
Let’s see how to come up with the value of the resistor! If your model for the driver is a constant resistor one, the calculations are very simple: you simply express the required resistance from the on-time or off-time equations (here I’ll use the on-time one):
ton = –(Rsource+Rg)*Cgate * ln(1-Vgate/Vsource)
so the needed series resistance is:
Rg = -ton/(Cgate * ln(1-Vgate/Vsource))-Rsource
Note that if you do the same calculations for toff, you usually get a different Rg value. Since you need to select a single value, it means that you can’t independently control the on- and off-times.
If you used the combined current-source/linear model, you have a bit harder time, because first you have to figure out how long does the driver stay in current-source mode. The switch-over happens when the drive voltage is at it’s knee point – 1.4V or 2.9V in our case. However at that point the series resistor drop VRg = Rg*Isource voltage and only the rest is on the capacitor. So the time it takes to get out of the current-source region is this:
ton_current_source = (Vknee_on – VRg)*Cgate/Isource
putting the above value in for VRg and doing some simplifications, we get:
ton_current_source = (Vknee_on/Isource – Rg)*Cgate
Similarly the time it takes to get out of the current-sink region for the turn-off time is:
toff_current_sink = (Vsource/Isink-Vknee_off/Isink-Rg)*Cgate
After that time, the driver is in its linear (constant resistance) mode, so the previous equations can be used. The total turn-on and –off times for this approximation are the following:
ton = (Vknee_on/Isource – Rg)*Cgate – (Rsource + Rg)*Cgate * ln(1-(Vgate-Vknee_on)/(Vsource-Vknee_on))
toff = (Vsource/Isink-Vknee_off/Isink-Rg)*Cgate – (Rsink + Rg)*Cgate * ln(Vth/Vknee)
But what is the right turn-on or -off time after all?
After all this math you might ask this question. The problem is that there isn’t a clear-cut answer. The reasons you might want to lower the transients are the following:
- Reduced heat dissipation on the MOSFETs
- More precise PWM control of the motor (the bridge spends less time in the not-so-well-defined transient states)
At the same time there are reasons to make the transients longer as well:
- The faster the transient is, the faster the catch diodes need to be
- Fast transients generate a lot of EMI noise
- Fast transients need high(er) current drivers
All in all, H-bridges are not the most demanding circuits as far as transient times are concerned: you’ve seen that a single AHC-series gate can pretty comfortably create sub-microsecond turn-on and –off times for a rather large FET. My guideline is that I try to keep the transient times to around 0.5-1% of the cycle time. This means that for a 20kHz bridge, I like to see 250-500ns transient times. This is a much more serious problem for higher switching frequencies that are normally found in high-power DC/DC converters, like PC motherboards.
In the following I will only deal with one-half of the bridge. The second half needs identical treatment, so I’m going to ignore that for a while. On the low-side, we only have one type of device to deal with: N-channel FETs. These need a low voltage to turn them off, and a higher voltage (typically in the 5…15V range) to turn them fully on. The question is: what to put in the place of the mystery circuit:
The simplest drive circuitry: none
For very simple, low-voltage designs, they might be completely missing, and the FETs are directly driven by logic level signals.
This technique however only works under limited circumstances:
- You have to make sure that the output voltages of the digital logic are in fact capable of turning the FET fully on. This was true in out previous example, but if you’ve used lower-voltage logic (3.3V or even lower) or wanted to have higher currents through the bridge, it would not have been the case
- The logic output has enough current to generate the required turn-on and –off times. This is especially important for logic output with asymmetrical drive capabilities, like open-drain CMOS outputs or TTL chips.
Higher current drivers
If for the above reasons, you want to have a driver that can provide more current (but you’re still fine with the limited output voltage range), you can still use the complementer driver configuration, just use larger FETs, with lower rdson.
Alternatively, you can gang together several output buffers from standard CMOS devices to increase the drive capability that way, for example by connecting all six of the available inverters in an 74AHC04 together:
So far we’ve only talked about low-side drivers where the voltage level of the gate-drive needed was within the range of standard digital logic. We’ve seen that – at least in that one example – a standard 5V digital logic gate works reasonably well for closing a relatively large MOSFET. As lower voltage (3.3V and below) digital standards gain popularity or if you try to increase the current capability of the bridge, you’ll find pretty quickly that direct logic level drive is inadequate.
When the gate-driver voltage of the FET is higher than your digital supply, at least a level-shifter will be needed in order to be able to drive the device. One of the simplest level shifters is this:
Here, the gate of the small-signal N-FET is driven by a suitable logic signal (and a logic level signal can easily turn this N-FET on) and the drain of it is pulled up to the gate-drive power supply, Vdrive. When the FET is off (the gate is driven to logic ‘0’), the output will be pulled to Vdrive by Rup. When the gate is driven to logic level ‘1’, the FET turns on, and pulls the output to 0V. So in fact, the output is the logical inverse of the input, but the voltage levels are changed to 0 and Vdrive.
The complication however is this: the drive strength (or current-delivery capability) of this level-shifter is significantly different in the ‘high’ and the ‘low’ case. When it drives low, its output resistance is pretty much rdson of the FET. When the output is high, it’s resistance is Rup. However Rup must be significantly higher than rdson otherwise the low-level output voltage would not be close to 0V. This in turn means that the turn-on time (which is determined by rdson for a P-FET) will be significantly – maybe even an order of magnitude – lower than the turn-off time, which is determined by Rup. This imbalance complicates shoot-through protection quite a bit and makes it very hard to turn the driven power FET off fast enough.
To overcome this problem, an complementer driver stage can be added between the level shifter and the power-FET:
This stage will make both the high- and low-level drive strength roughly equal, consequently making the turn-on and –off times much closer to one another.
High-side P-MOS drivers
So far we’ve only talked about driving N-MOS devices and driving them on the low-side. Let’s consider now the high-side drivers, first for P-MOS devices:
This configuration present some complications: P-MOS transistors are open (non-conducting) when their gate is at close to the same potential as their source, and closed (conducting) when the gate is at a significantly lower potential, -5…-15V lower. This means that in order to completely turn off a high-side P-FET we’ll have to drive it’s gate as high as it’s source, which is connected to the power supply. To turn the FET on, we have to lower the gate voltage by 5…15V below Vbat.
All the drive circuits we’ve discussed before can be used for high-side P-FETs with the following change: you have to power the driver stage from the same voltage as the bridge is operating on, that is Vbat. That way, the high-level output voltage will be Vbat, which will turn the P-FET off properly, and the low-level output voltage will be 0, that is almost always enough to turn the FET on. (You might have problems with extremely low Vbat voltages, where you would have to drive the gate to a negative voltage to turn the FET on properly. This however is a rare enough case to ignore simply because high-current H-bridges usually operate at higher voltages and low-voltage H-bridges have low-enough currents that a small logic-level FET can be used in them that can be turned on by -Vbat.)
Direct logic drive complications
The additional limitation of the driver operating from Vbat has a significant consequence for direct logic-gate driven bridges: a simple AHC series gate, like the one we’ve used before will only be able to function in this role if the bridge power supply is lower than the maximum supply the gate itself can be operated from, that is, less than 5V. This is a very serious limitation as most bridges but the smallest ones operate from higher voltages to maximize power delivery without requiring enormous currents.
With all that, for small motors this approach can result in a good, cheap solution. For a practical example, take a look at the Servo Brain µModule project.
High-voltage drive complications
One of the major contributors to premature MOSFET deaths is gate-oxide break-down. The major cause of the breakdown is too high gate-source voltage on a MOSFET. The datasheets always specify this value, and for power MOSFETs at least the value is usually +/-20V. Getting out of this region will very quickly destroy the FET.
This presents a problem for the high-side P-MOS drivers: if Vbat is higher than 20V, we can’t allow the gate drive to go down to 0V any more for low levels. It can go only as low as – say – Vbat-15V to allow for some safety margin as well. This is usually accomplished by adding a Zener diode to the drive circuit:
If you set the Zener voltage to about 15V, it will limit your voltage difference between the output and Vbat to be within the safe limits.
Similar limitations are needed on the low-side as well, if your driver works from Vbat and not from a separate power supply.
N-MOS high-side drive circuits
So far we’ve only discussed driving P-MOS devices on the high-side. With all the complexities of level-shifting and voltage-limiting, P-MOS drivers are still simpler than drivers for an N-channel device.
The reason is the following: The source of an N-channel device on the high-side has to be connected to the motor terminal and its drain to the power supply, otherwise the body-diode would be forward-biased and would always conduct. To turn off an N-MOS device in that configuration, you can connect the gate to ground or to the source: gate-source voltage is going to be below or equal to 0. But where to connect the gate to turn on the device? The power supply is not enough, since, if the device is already conducting, it’s source and drain are roughly at the same potential. As the drain is connected to power, the source will be at that level as well, but than gate should be higher than that to keep the device on. We’ve seen that the gate should be at minimum 4.5V higher for our example above, and for some other devices maybe as much as 10-15V higher.
As Vbat is usually the highest voltage directly available in a system, this voltage needs to be generated. In most cases some kind of a charge-pump is used for that generation, mostly in a boot-strapped configuration:
While actual implementations could be quite a bit more complex, I will use this simplified variant to explain how things work. These circuits are usually operated form a voltage supply (Vcc) somewhere between 8 and 15V, for our discussion let’s say it’s working from 12V.
This high-side driver shows strong similarities to the P-MOS high-side drivers we’ve discussed before, there are significant differences. While it also consists of a level-shifter (Q3, R1) followed by a C-MOS driver stage (Q4, Q5), this stage is neither grounded nor is connected to power. The lower leg of it is connected to the middle terminal of the bridge, or more importantly to the source of the power FET it drives, Q1. This means that the low-level output voltage of this stage (Vhi_drv) will be the same potential that the source of Q1 is, whatever that happens to be.
Let’s now see, what the voltage (Vboot) of the higher leg of the driver – that determines the high-level output voltage – is! To understand the operation of the circuit you’ll have to imagine that both the high- and the low-sides are driven by a PWM signal. We close Q2 for some portion of every cycle, and Q1 for the rest (not counting shoot-through protection for a minute).
For the part of the cycle, when Q2 conducts, the output terminal voltage (Vout) is 0V, or very close to it. Since one side of Cboot is connected to this node, it is also grounded. Dboot, which is connected between Vcc and the other side of Cboot will make sure that Cboot is charged up to Vcc:
This of course also means that Vboot is equal to Vcc, 12V in our example. When it comes to turning Q2 off, Vout starts floating. Depending on what the motor, and the other side of the bridge does, either D1 or D2 will open and continue conducting the motor current.
If D2 openes, Vout would stay at 0V (actually it would go slightly negative for D2 to conduct, but let’s ignore that for now), so Cboot and Vboot stays as they were: charged up to Vcc, or 12V higher than Vout.
If we wanted to turn Q1 on at this point, Q4 can easily drive it’s gate 12V higher than it’s source terminal voltage (Vout), so we can clearly turn it on.
If however D1 starts conducting after we turned Q2 on, Vout rises to Vbat (again, slightly higher, to forward-bias the diode, but I’ll ignore that here). When that happens – since the voltage across Cboot can’t change abruptly – Vboot has to rise and reach Vbat+Vcc. Normally, Cboot would discharge quickly towards Vcc, but in our case Dboot closes and lets Vboot rise as high as it wishes:
At that point Vout is at Vbat and Vboot is higher than that by Vcc (12V). If we wanted to turn Q1 on at this point, we can still do it: the high-level output voltage of the driver (Vboot) is 12V higher than the source voltage of Q1, as it is connected to Vout.
All in all, Cboot and Dboot will make sure that Vboot is always at a higher voltage than Vout by Vcc. Or at least most of the time. The problem is that whenever Vboot is higher than Vcc, the only thing that keeps it at that level is the charge kept in Cboot. Any current that’s flowing out of that node will discharge the capacitor and eventually bring back Vboot to only Vcc. In our simple circuit, most of that current will flow through R1, but even if we solved that, other leakage currents through the various components will eventually do that. It takes a long time, probably seconds, but inevitably it will happen. What it means is that, while this circuit can certainly turn Q1 on, it can’t keep it turned on indefinitely.
The most important consequence is that bridges driven by this type of driver can’t operate at 100% duty-cycle: you’ll have to give some in every cycle for Cboot to re-charge.
As far as drive modes go, the circuit doesn’t put a significant limitation on the number of options available. For lock anti-phase drive, all four FETs are switching, so there is not problem at all, but for the two sign-magnitude drives, you’ll have to make sure that the FET that’s continuously on is on the low-side.
Another problem worth mentioning is this: when you try to turn Q1 on, that is you turn Q4 on, you basically connect Cboot and the gate-capacitance of Q1 in parallel. If Dboot is closed, so the only place to get charge to the gate is from Cboot, you are essentially just re-distributing the charge between the two capacitors. As that happens, the voltage on them will get lower, and the gate-voltage you can achieve depends on the ratio of the two capacitances:
Vgate = Vcc * Cboot / (Cboot + Cgate)
What this means is that if you want to make sure that Vgate is – let’s say – within 10% of Vcc, you have to make sure that Cboot is about an order of magnitude higher than the gate-capacitance of Q1. We’ve seen that the gate-capacitance of large FETs can be several nF, so Cboot should be in the 47-100nF range for those devices.
The last thing to talk about is that as the bridge is switching, Dboot keeps opening to top-up Cboot. But how much current will flow through it? As I’ve drawn the circuit above, the only thing limiting this current is the internal resistance of Dboot and the wires connecting them. All in all, there could be a significant current-spike on Vcc through Dboot due to the operation of the charge-pump. The power supply generating Vcc has a finite internal resistance, so this current-spike will translate into a periodic voltage drop on Vcc. To prevent that, usually a resistor is connected in series with Dboot to control the current flowing in the capacitor. It’s value is determined to make sure that you can completely re-charge Cboot even under worst-case duty-cycle conditions:
Let’s say you allow for a maximum of 99% duty cycle, your gate capacitance is 5nF, Cboot is 100nF, Vcc is 12V and the operating frequency of the bridge is 20kHz. This means that you will charge the gate of Q1 up to 12V (disregarding now the voltage drop on Dboot and due to the charge-redistribution phenomena we’ve discussed above) 20000 times a second. Each time you charge the capacitor up, you need 5nF * 12V = 60nQ of charge. Since you do that 20000 times a second, the total charge transferred to the capacitor over a second is 1.2mQ, or in other words, your average gate-current is 1.2mA.
Let’s say (due to charge-redistribution and other leakage paths) under worst-case conditions Cboot looses 10% of its charge during the on-time. This results in a 1.2V drop on Vboot, that needs to be replenished during the off-time, which is (under worst-case conditions) 1% of the total cycle-time, or 500ns. To charge a capacitor of 100nF up by 1.2V in 500ns, you need 0.24A of (peak) charge current to do it.
From this quick calculation you see that the peak current (flowing through Rboot and Dboot) can be quite large compared to the modest average current flowing to the gate of Q1. This is important as this high current will stress your power delivery network, and can be a strong noise source for other parts of your design.
If you are curious, there’s plenty of more detail about these boot-strap circuits in device datasheets and application notes, like this one: http://www.fairchildsemi.com/an/AN/AN-6076.pdf
We haven’t talked much about that so far, but the fact is that H-bridges and step-down DC/DC converters share a lot in common. So much so, that the driver circuits we’ve talked about here are the same that people use for high-current, synchronous DC/DC converters. Such converters are in use on PC motherboards these days, and that brought about an abundance of cheap and high-performance half-bridge drivers. These are almost exclusively of the boot-strap-based dual-N-channel MOSFET driver kind, but are equipped with additional goodies, like shoot-through protection, various input configurations, several voltage options, enable pins, built-in boost diode etc. They usually come in SO-8 packages, but of course other options are also available. You would need to use two of them to make a full bridge driver. Some examples include the L6743Q or L6387A from ST, the ADP3120A from OnSemi. You can also find full H-bridge drivers like the venerable – and expensive – HIP4081A from Intersil.
This was a loooong article I have to admit, but hopefully it gives you some background into the design challenges of the drive circuitry of H-bridges. For all but the most simple applications, specialized drive circuitry is needed as while low-side drive is quite often possible from simple logic signals, high-side drive is usually more involved. Today, the availability of cheap, boot-strapped half-bridge driver ICs makes all N-channel bridges a very attractive design option.
Now, that we’ve covered the basic construction of the bridges and their associated drive circuits, in the next installment of the series, we will look into the control of the bridge and some interesting variations on the previously established sign-magnitude and asynchronous sign-magnitude drive options.
Nice writeup! I just started thinking about making a thermoelectric cooler/heater and this was exactly what I needed.
Very informative! Thanks to your series of articles! 🙂
You refer to Q7 and Q8 in your “N-MOS high-side drive circuits” discussion yet they’re not anywhere in the figures. Can you please clarify what you mean by Q7 and Q8 then?
Oops, thanks for noting that! I’ve changed the pictures, but forgot to update the associated text. Now it should be fixed.
This article is just what I needed. I’m designing an electric motorcycle using a PWM-controlled 3-phase AC induction motor. I have a degree in EE, but have not kept up with what has been developing in the power semiconductor industry. Thanks for publishing this.
Thank you very much. Really very informative!
I just have a question about N-MOS high-side drive circuits :
Is it possible to apply a second voltage higher than V_bat from a second power supply. I mean if the main power supply is 40v ,there should be another one higher no more than 20v (55v) to drive the N-MOS high-side gate?I did the simulation and it worked.. I will try that sooner in real.
while googling I didn’t find info about this.. does it have any disadvantages apart cost?? like in turn off, turn on shoot through…?
Don’t try it! It will blow your FET.
Well, actually it is possible to do and for low voltages that’s quite common. For example (DC-DC power supplies are actually quite close to H-bridges in this regard) old PC motherboards, where the CPU core voltage was regulated down from 5V, the high-side drivers were often driven from 12V. Exactly what you’re saying.
Doing this above, say 20V however is getting tricky: the problem is that the source of the high-side N-FET is connected to the load. When the low-side is on, it drags the high-side source to (close to) GND. Now, when you get to turn on the high-side FET, you apply in your example 50V to the gate, while the source is at GND. Not many MOSFETs can survive that, most of them are specified for a Vgs no more than +-20V, maybe even less.
In other words, you will only be able to use your technique when Vbat (the power supply to the bridge and the load) is less than Vgs_max-Vgs_on. To turn a high-power MOSFET on, you need a Vgs ~= 10V or so, and if Vgs_max is (say) 20V, than you can only use your idea with Vbat <= 10V. Give some safety margins, you get Vbat <= 5V. That's the reason the old PC motherboards were done that way. When you have a Vbat that's higher than that, you'll have to somehow 'float' the gate drive voltage relative to Vs (Vout). The boost circuits most commonly used (the one I'm showing in the article) achieve that: Vboot ~= Vout + Vcc. Another way of achieving the same is to connect a zenner diode with a brake-down voltage of say 10V between the gate and the source of the high-side FET. With the appropriately sized Rg, this circuit also works: you limit the voltage on the gate of the MOSFET dynamically relative to its source. The (potential) problem with this is that when the zenner conducts it might present a high current load to the drive - the reason you need to be careful about the value of Rg. Lastly, in many applications Vbat is the highest available voltage, so getting an even higher one is problematic.
Really I thank you very much for such information..and your answer. I spent last night in your site reading and reading..till now I am always connected to it. I have many tabs in my firefox :).I even repeated reading and I will do till I understand.
What I need about mosfet and h-bridge is really explained very well and in an easy way.. thanks again for your answer.
About H BRIDGE I don’t want ready made IC to drive the N-MOS.i want to experiment by myself like you did :).I want to drive bipolar stepper motor with all possible options like chopper and microstep but without ready made IC.and with variable powerfull power supply till 50v to test various stepper motors, I want use only P&N MOS as driver. Before being in your site I was reading a lot elsewhere,but last night your site explained to me many things ,
and I know now why I already blew many FETs
in “High-voltage drive complications” you said “if Vbat is higher than 20V, we can’t allow the gate drive to go down to 0V any more for low levels. It can go only as low as – say – Vbat-15V to allow for some safety margin as well”.
It’s ok. but the stage before that which is “the complementer CMOS driver” both MOS will not be protected if VBAT IS higher than 20V, right?
If yes is there a solution for this? like adding zener also?
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I’ve been working on something similar, and posted it on the Arduino Forums for extra tips, as well as fixing an enormous D-S voltage drop I experience in simulation.
I’m getting a lot of flak about tying the gates together, and everyone is saying my schematic is total garbage. I actually haven’t received any of the information I was looking for. I’m getting some good information, like a potential short caused by the two mosfets switching simultaneously. But other than that, the Arduino Forums, in my experience, are more likely to insult you for trying.
Your circuit in fact have a few problems, but the forum you’ve posted on seems to have been helpful. The first response lists the problems: shoot-through and gate-resistors. I suggest you take a look at this piece of the series: http://www.modularcircuits.com/blog/articles/h-bridge-secrets/h-bridge_drivers/.
very interesting and useful article! My congratulations.
Just one note regarding the high side PMOS driver.
I’ve used a different (actually quite common) technique: starting from a standard 5V logic buffer (with all the output connected in parallel like in your 74AHC04 example), I’ve first AC-coupled the output and then hooked it to the Vbat rail through a diode (plus some protection/limiting resistors) to clamp any voltage over Vbat; this way the VGS is -5V and the PMOS is properly turned on/off. This seems to work pretty fine in simulations and overtakes the asymmetrical driver strength issue due to any external resistor
Thank you for your feedback!
You are absolutely right, that technique works, as long as you have a constant pulse train driving the high-side FETs. I should update the article.
for what I know the main drawback of the bootstrap-like drivers is the negative voltage spikes they can tolerate on the source terminal, so basically they cannot be used at all in an application where you need split supply (positive and negative) at the bridge legs.
Are you aware of any suitable drivers for such kind of applications? I found some parts form IR (like this: http://www.irf.com/product-info/datasheets/data/irs20965spbf.pdf) specifically suited for D-class amp applications, but I was wandering if any other standard drivers were available.
In short, no. But to my untrained eyes, it seems that it might be easier to use a high-voltage driver with it’s GND-reference tied to the negative supply. This of course creates a need for a level-shifter on the input-side, but that seems to me to be an easier problem to solve then the bridge-drive.
I really like this article, it’s very well written and really beginner friendly!
In calculating turn-on and turn-off times part, you say:
“You can easily see that for the case of driving high voltages, the current source is at around 17mA, and the resistance is around 100Ω. When the output drives low, it can output 21mA and has roughly 70Ω resistance. (It is typical that an output stage has a somewhat weaker high-side driver, being a P-MOS device.)”
Where do you read that the resistance is around 100 ohms? I cannot undertand if you see it somewhere on the chart or I just missed an obvious calculation you made?
The resistance is related to the steepness of the linear portion. In this example, if the current drawn is around 10mA, the voltage drop on the output is around 1V. R = U/I = 1V/10mA = 100Ohm.
I hope this helps,
Yes, now I understand!
Thanks again 🙂
I have to questions:
1- How do we find the output resistance of gate driver that does not provide you with output voltage and current in the same graph? for example this gate drive IR2106, I calculated the output resistance from the static characteristic, is that correct?
2- Why do we have to operate in the linear region not the saturation? couple of website they recommended to operate in saturation region. I have been looking for the purpose and I barely found a solid answer, could you please talk about it a little in deep ? I see why we have to operate in the lower side since we do not have negative voltage applied on the gate (…etc Vd = 0V, Vs = 0 and Vg = 0V or 5V) but the high side could be operated in saturation (…etc Vd = 12V, Vs = 12 and Vg =<25).
1 – yes, that’s the best you can probably go by and it’s a good first-order estimate.
2 – operating in a saturation region is sub-optimal: notice how the curve drops lower then a straight line. That means that the effective resistance of the FET increases, so you burn more and more power on the FET, making it hotter and lowering bridge efficiency. The curve also quickly levels off at a constant current. That means you can’t increase the output power of the bridge any further.
One benefit you get from this effect is built-in current-limiting: what happens is that as the motor current increases during the on-time, you reach saturation where the FET will start limiting current. This in turn will limit torque, which is beneficial in most applications. For example, you don’t want your motor to shier cogs off of your drive-train. The down-side is – again – efficiency: the FET does this in ‘linear’ mode, that is it limits the current by by increasing it’s source-drain voltage drop, thus burning more power.
All in all, while you probably do want current-limiting in your design, it’s best left to the control circuit. That way you that can do it in ‘switched’ mode, not affecting efficiency.
I really enjoyed your article! But I have a question. It seems that in many places in the text you refer to the device being “open” or “opening the device” when it seems as though you are talking about turning the devices “on”. It seems like “on” would be appropriate, and “open” would be analogous to “off”. Am I missing something here?
It’s a bit confusing, I admit. I’ve cleaned up the article. Thanks for the comment!
Quietly often you find drivers with a low output resistance but a limited current capability, isn’t it better to add a resistor between the output of the driver and the gate of the mosfet? So you don’t end up with burning them
The series resistor is more to control the turn-on and turn-off timing then limiting gate drive current – though that’s one of the effects. The best practice is to determine the turn-on and turn-off times you need, figure out the drive current you need to manage that (it depends on the gate capacitance and voltage too), than choose a driver that can deliver that current. Trying to make an under-powered driver work is asking for trouble.
Hi my friend, im running the boost trap circuit for switching high side but a have a problem when i set up de Vbat over 70Vdc, i have a bipolar power source 150Vdc and -150Vdc. I dont know why its fine below 70Vdc. i would like send you the diagram.
Please do send a diagram. From this description I have no idea what the problem could be.
‘zenner’ ?? Zener.
The complementer CMOS driver , they use small FETs to drive bigger FET right? Then…
If that small FETs have low Rds , for example BSL316C L6327 , Rds(on) 171mOhm will be problem?
Or BSL316C L6327 they have both P and N , 177mOhm then will be problem?
Suppose Battery = 12VDC
motor stall current = 1A
The calculate is I=Vbat/Rds then Ipeek = 12Vdc/(0.177+0.177) = 33.9A but that for short time.
ton of P – N difference is 5ns , 3.4ns so it difference = 1.6ns , tooff is 14.3ns, 5.6ns so the difference is 8.6ns.
If I try P= 12VDCx12DC/(0.177+0.177) x 8.6ns = 3.49uWatt
Meaning current is peek in short time (transition period) , so heat dissipation is less…. not to be problem. Am I right or wrong?
Is that correct?
Point is in my place , to find small P-FET with higher Rds is not easy. They only have P-Power FET. If this not work I might have to online order cost more money from some distant place.
Well but LTspice show ugly spike current look horrible in low Rds FETs in complement when in transition
You probably see shoot-through. The high Rds ON FET will mask that problem as the shoot-through current is limited by the on-resistance of the FET. You have to tune the drive of the FETs so they don’t overlap.
What if I use push-pull BJTto drive FET? So that I can avoid another short-trough in FET.
Push-pull will follow base voltage then I just add voltage shift by 1 more FET. Some thing like this picture.
What you think about it?
I have a question on cascading an H bridge. For a DCC (model train) decoder, I need a larger current then the “standard” bridge of that decoder provides.
Is it possible to cascade an H bridge that can switch the current (e.g. 3A) to the orginal H-bridge which provides an PWM motor signal (max 1A)?
Any special considerations on “hooking” them up, so that the motor is floating or uses breaking when the original PWM signal send to the normal (low current) motor reflects this?
Cascading H-bridges is a really bad idea. For one, it will limit current delivery to the lowest of any of the bridges. On top of that it will most likely not work at all. Putting bridges in parallel might work, but there are a lot of pit-falls there as well, and driving them all with the same PWM input is a must. The best way though is to have a single H-bridge, capable of driving the right amount of current. Since 3A and 1A are not all that different, can you maybe upgrade the power transistors in your old bridge to help with the increased current?
Hi Andras, thanks for looking into this!
I will inspect the type of FETS used in the DCC decoder, then mount stronger FETS either in place, or on a separated board and use them. As you said, the current requirements are not that drastically different, so the driver of the gates is probably capable of driving the more powerfull FETS. In fact, I might use the integrated H bridge that I ordered: half of an L298N.
If I understand your answer correctly, you recommend to remove the FETS and protection diodes on the DCC decoder driver and then feed the DCC signals originally going to the gates of the (removed) FETS to the inputs of the H bridge: half of an L298N in my case.
I have a unique problem I would like insight too. It has been an electronic mystery to me – and ideas are running short. I have an H-Bridge design I am looking into. The rate of failure is less than 2%, but they want a fix. The device can run from a battery or wall adapter. When it fails, IT IS ALWAYS THE SAME lower N and not the P. There are several interesting things about this failure. 1. The N has a higher Id rating than that of the P. 2. The bridge suffers from a conduction issue in its design. The switching on FETs input C feeds back to distort the unintended off leg – making for momentary conduction. Try as I might, though this happens ALL the time – I have been unable to prove this is the issue. And it does happen on both sides. 3. When the N fails it always fails with a D-S short, but the G to D and G to S are also very low (typically less than 10 ohms). 4. The bridge drives a motor. The motor stalled can only draw .5A. When operated from wall adapter the wall adapter does not supply enough current even at its peak (SC) to be the issue. The SC current peaks at about 4.2A and the wall adapter folds back. What would be causes whereby I have the same FET to fail and not others.
Of course it’s very difficult to give any advise without seeing the problem and doing experiments, but my first hunch would be that you violate the Vgs maximum rating on the device. MOSFETs are very sensitive to this and even a momentary violation (that can happen due to capacitive coupling for example) can destroy the device. If I’m right (and as I’ve said, I could easily not be), the mitigation might be that you artificially decrease the impedance of the gate node of the FET so that the capacitive coupling doesn’t build up dangerously high voltages. You can do that by connecting a resistor between the FETs gate and source.
As to why (again, predicated on me being right about the cause) this only impacts the low-side: P-channel MOSFETs for the same current rating (Rdson) are typically bigger then the equivalent N-channel device. This in turn means higher gate-capacitance. If there is indeed capacitive coupling, the parasitic capacitance and the gate capacitance forms a capacitive divider, which would result in a lower peak voltage on the P-channel part then in the N-channel for the same amount of aggression. So the N-channel device would see a Vgs violation sooner than the P-channel part would be.
I hope this helps,
A million thanks for taking my question!!! Regarding paragraph 1 of your response a resistor added between the FET D and S, would have to be a very high value to not look like a leakage on condition. To decrease coupling back into the control circuit I introduced a resistor in the gate of the FET – there a sweet spot that has to be found that reduces the feedback, but does not overly slow the FET at stated PWM. It worked well in circuit and in simulation – though I would admit it looks a little strange in schematic. All the same my real goal is to find root cause of the problem.
Regarding the second part of your response – I’m not quite following you. Are you referring to a coupling path at the point of where the N and P Ds meet feeding back onto the Gs of said devices with the transient coming from the motor, or are you referring to a transient coming from the supply and being passed more effectively to the gate of the N. I am missing the cap divider concept here – assuming the parasitic cap you make reference to is the Cgd and Cgs
Lastly not only is it the N that is failing it is always the same N (not the other).
The idea is connect the resistor between the *gate* and the source, not the drain. It appears you’re already working on a similar solution.
The second paragraph was a theory as to why the low-side FET is going bust. If you have noise coupling into the gate of (either) FETs capacitively, there is always a capacitive divider between that parasitic coupling capacitance and the gate capacitance (along with any other things connected to the gate, for example the driver output capacitance).
For the same low-side FET to fail all the time – to state the obvious – there must be an asymmetry somewhere in the system. This might not be in the circuit though: for example if you mostly drive the motor in one direction, the circuit is used in an asymmetrical way, even if it itself is totally symmetrical.
Boa noite, tenho um Easy driver A3967 com corrente mínima de 150mA, acontece que meu motor é um PM20T-36, com corrente máxima de 30mA, desejo acionar ele em microstep, posso associar resistências em série para funcionar ele? Haveria algum driver para esta corrente de 30mA, existe alguma solução para o meu problema. Thanksss
You are asking a stepper-motor question, a subject I’m not familiar with. So sorry, I can’t really help.
The current regulation of that driver will always keep it at the setted value despite of the resistors that you put in series with the motor
Hello, Why the interchange of the values of Isource and Isink in determining the turn on time and turn off time?
ton = 4.5V*1585pF/21mA = 339ns instead of 17mA
toff = (4.5V-1.2V)*1585pF/17mA = 307ns instead of 21mA.
Look forward to Hearing from you
Good point, and it was a mistake. Fixed the math and thanks for reporting it!
The same also for this;
ton = –70Ω*1585pF * ln(1-4.5V/5V) = 252ns
toff = –100Ω*1585pF * ln(1.2V/5V) = 220ns
Why the interchnage of the resistance value?
Good point, and it was a mistake. Fixed the math and thanks for reporting it!