The UnIC project arrived at a major milestone: after some inordinate amount of work, I managed to track down the last remaining (known) problem with the FPGA code for the Z80 emulation.
There were two pieces to this puzzle: the Shadow Tracer board and FPGA core that allowed me to quickly identify discrepancies between the Z80 original and my (well, T80-based, so it really is a community effort) implementation.
This really simple PCB allows for parallel execution of both designs while comparing and flagging any differences:
The PCB was manufactured by my sponsor, PCBWay. They did a great job on making the boards for me quickly and in high quality. They also can do all sorts of other jobs, such as PCB assembly, flex or rigid-flex PCB manufacturing, even 3D printing and injection molding. I haven’t used those services yet, but it if that is what you need, give them a visit!
The second part was doggedly going after the problems as they arose until I was left with the true issue: a bug in the T80 NMI handling that allowed for a nasty priority-inversion and a loss of an NMI event.
I’m a bit cautious about opening the champagne bottle yet though. I want to build yet another board, one that would hopefully allow to truly check for all remaining differences:
I suspect it will uncover some discrepancies, hopefully nothing major. But, for the first time in this long project, I am at a point where I’m not aware of any issues. Let me tell you, it feels nice!
I have a (silly?) idea of how to deal with non-deterministic sampling of async signals: replicate the T80 core twice inside the FPFA. This way, the two T80s can sample the inputs at slightly different points in time and take diverging paths when there is a timing violation. Once there is an observable difference between the outputs of the Z80 and one of the T80s, overwrite its state with a copy of the other. The last step will probably require extensive modification of the T80 code base, but it should allow async signal handling without the comparator special casing or additional synchronization hardware.