Introduction

In the previous chapter, I discussed my buck regulator that I will sprinkle around the design to generate the 3.3V logic supply in enough copies that the per regulator current is below five amps or so. In this chapter, let’s look at the +/-15V analog supply. These are going to power all the sense amplifiers in the design. Simulating them, I get the following:

Sense amp	Number of instances	+15V power per instance [mA]	-15V power per instance [mA]
Tape	4	25	15
Core	16	40	15
ROM	16	55	45
TOTAL		1620	1020

To be on the safe side and not over-complicate our lives, let’s go with 2A as the design target for both.

As I have said before, I intend to sub-regulate these supplies from some higher voltage using linear regulators. Since I don’t want to get the linear regulators’ power transistors into saturation, I believe, I’ll need at least 1V drop on these, so the input supply should be at least 16V. Technically, for the +15V at least, one could use the 20V supply directly, however a 5V drop at 2A means a 10W heat dissipation on this regulator, which I don’t really like. I could also crank the analog supply voltage of the sense amps to something like 18-19V and just move on. Even then though, I still need the negative supply somehow.

For 2A, switched capacitor designs are pretty much out of question, so I’m left with either an inverting converter a fly-back or a forward regulator. After some tinkering, I like the forward regulator topology the best; the others have incredibly high peak inductor currents. There’s a good appnote on this topology from Infineon.

The first problem here is to find the appropriate transformer. Probably the best place to look form them is this Digikey category. What we need is three windings with a winding ratio of 1:2:2 or similar. The PA3856.006NL seems like a rather good match. At $3.52, not even all that expensive, given I only need one. Actually, the PA3856.007NL would probably be even better, but that’s a unicorn that only Mouser carries and even Pulse, the manufacturer doesn’t seem to have it in their database. Weird…

So let’s try to use the non-unicorn variant, the PA3856.006NL. Here’s what the datasheet says about it:

First, I was looking at this basic topology for a forward converter:

As it happens, the chosen transformer has an extra winding for this (called reset) coil, that’s connected through D3.

Let’s think about this design for a minute! As all of these isolated designs, it has no way of transferring the ‘DC’ component of the control signal, which means that duty cycles beyond 50% make no sense, in fact would just crank the transformer core into saturation. I will need to make sure, I adhere to that limit. There will be consequences when designing the control logic for sure.

For now, though, let’s try to model this up in LTSpice. To do that, we need to determine the k factor of the transformer, however the datasheet only specifies the leakage inductance. If I understand things correctly, this is how the two quantities relate to one another:

For us, Lp is 128uH and Lp^ro is 0.15uH, which would give us a k value of 0.9988. This is so close to 1 that I will simply ignore it for now at least.

Unfortunately, after modeling this bad boy, it seems, I’ll need to increase the input voltage spec to about 30V to get the desired +/-18V on the output at 1.5A current draw. That’s a bit of a bummer. The reason for that, is that (with the primary and the reset coils not having a 1:1 turns ration), I can’t even get to 50% duty-cycle. Not in this topology at least. After tooling around in a bunch of ATX power supplies, another, alternative topology emerged:

This is further documented here. It’s pretty much the same idea as the one before, just uses the same coil for reset. With the particular transformer I plan on using this is crucial, because it allows me to increase the duty cycle to 50%, which in turn allows me to lower the input voltage back to 20V and still get ~20V output, even under heavy (2A) load.

Simulation gets me this result:

Now, of course there’s no control loop here, so the overshoot is not surprising. I’m also wondering if I need a control loop at all. Here’s the reasoning: if I sub-regulate this supply to +/-18V with a linear regulator anyway, do I care how precisely the output of the switcher is set? Granted, under light loads, the output voltage is about double then this:

Still, do I care? As long as the regulator can take 40V (make it 50 to be on the safe side) inputs, the heat dissipation shouldn’t be terrible: by definition the current is low here. Actually, let’s calculate!

I want +/-15V output. So, in the 2A case, I have 5V drop, leading to 10W dissipated (ouch, BTW!). In the light load case, I have 0.05A load and 25V drop, so the power consumption is only 1.25W on the regulator.

So yeah, if I can dissipate 10W on these regulators, I don’t need to control the switcher at all and still get away by a supply variation of +/-10%.

Another note is that the peak input current is absolutely massive: around 14A. And this is at 500kHz switching rate. This will call for some carefully designed input filter (both in schematic and layout) to keep both the current and the EMI local.

Asymmetric loads

There is a bigger problem here though: if the output voltage depends on the load, then it means that asymmetrical loads lead to asymmetrical output voltages. Even if I do add a control loop, I can only control for one of the output voltages. But let’s stop here for a second! This problem exists for all such designs, for instance every single ATX power supply on the market. How do they do it? After all, they have all manner of output voltages with highly differing (and time-dependent) loads.

Looking at example after example, the idea that merged was this: make the output inductors coupled. Here’s a relatively readable variant, (from this collection):

This, being an isolated design has some other complexities around the primary gate-drive, but much of the general structure is the same. Importantly, you see how all the output inductors are coupled.

Let’s try this idea and couple the two output inductors:

Now, even with asymmetrical loads, the (eventual) output voltage ends up being symmetrical:

So, I’ll need to find a second transformer for this purpose. This doesn’t seem to be a big problem either, there are plenty available, the starting point is this Digikey page.

That takes care of the coupling of the outputs and – if I have some control at all – that will take care of regulation.

Plan of attack

First, I need to select the switches and their control. Then, I’ll need to devise an oscillator (with settable duty cycle) for the un-controlled setup. After that, I can start to think about the control loops and see how complex this whole mess becomes. So let’s get going!

FETs and their drive

Let’s start with the gate drive. This time, we have two switches to control: one on the high side, one on the low, both need to be turned on and off at the same time.

The first idea is something simple such as this:

Here, when Q1 conducts, it pulls its emitter and base close together, at first blush, to the same potential. Since R7 and R8 are the same value, that means that both emitter and collector are at roughly 10V. This is sufficient to turn both M1 and M2 on. When Q1 stops conducting, both gates are pulled to their respective rails by R7 and R8, turning the FETs off. Simple. The problem with this is the usual: using a resistor to drive (in one direction) the gate of a FET is going to be slow. Indeed, you can see the turn-off delay in the simulation:

This supposed to be a 50% duty cycle, 500kHz signal. Well, it’s not. But is that a problem? As long as we can get enough regulation out of this driver, it might not be problematic. What I’m not sure about is how to guarantee that duty cycle never goes beyond 50%, especially in light of this delay.

We can try to replace the BJT with a small-signal MOSFET to get rid of the saturation effect. We can also create dividers from R7 and R8: we don’t need 10V swing on the gates to turn the FETs on. 5V should be plenty:

Indeed, these changes help quite a bit:

Here, the blue curve is the drive input and the green one is the current on the load. It’s delayed, but pretty close to 50% in duty cycle. I think I’ll accept this.

Clock source

So now, I’ll need to make something that drives this … driver. Let’s start with a fixed frequency oscillator with adjustable duty cycle. Adjustable, because I’ll need to tune it to be slightly below 50%. Here’s the circuit I came up with:

Q11 with the help of D1 creates a roughly 5.5V, regulated supply for the oscillator. The oscillator itself is based on a very similar Schmidt trigger (M4, M5) design that I’ve used in my buck regulator. This time however, its input is fed by an RC timing circuit: C4 is charged through R10 and discharged through R35. Of course there need to be two transistors (M7 and M6) to control when charging or discharging happens. The two resistors, allow the control of the high- and low- time of the oscillation, thus giving me control over both frequency and duty-cycle. With the settings as they are, the circuit oscillates at around 500kHz with somewhat less than 33% duty cycle. This needs to be fine-tuned, obviously. Finally, M8 provides a level-shifter that can drive the gate of M3 from the previous driver circuit.

BTW: I just realized that I kept showing M1 with its drain and source swapped in the previous diagrams, well, that’s corrected here (interestingly it didn’t matter for a resistive load, but it does for an inductive one, that’s how I noticed it).

Putting this all together results in relatively temperature-independent, stable albeit somewhat low output voltage from the regulator:

Control

This might actually be good enough, if my input voltage is known and stable. I’ll just have to tune the duty cycle, a.k.a. the output voltage. However, let’s at least try to add control and see where we end up.

The idea is the following: if the output voltage is too high, we should just skip the on-cycle by preventing the driver (M4) from turning on. Don’t even try to adjust the oscillator or the duty cycle. Simply skip whole cycles! This way, we’re guaranteed that we will never violate the 50% duty cycle.

If you think about it, this is almost identical to bolting my hysteretic controller around the oscillator as an outer loop. Except, I don’t think I need hysteresis this time; the reaction time of the oscillator will take care of any instabilities. After some tinkering, this is what I came up with, and let me tell, you it’s a beast:

So, let’s go through this together! From left to right, D1 is our reference voltage. This, through Q11 is used to create a local power supply that’s independent of the input voltage. It’s also used through Q4 and eventually Q2 to create the reference voltage for the error comparator, which is Q1. The input to this comparator is an emitter follower made out of Q5, which in turn is fed by the feedback voltage. The use of so many transistors here makes the threshold voltage of the comparator temperature independent. C8 and R31 creates the soft-start R/C delay by slowly ramping the comparator reference. This is not ideal as we can’t really lower the comparator emitter to 0V (there’s one Vbe drop on Q2), but I think it’s going to be close enough. If not, I can use a circuit similar to what I have in the buck converter design for the cost of an extra transistor. The speed of the control loop can be adjusted by C7, but as it’s set currently (1pF) it’s as if it’s not even there. The output of the comparator is level-shifted to the right voltage levels (remember, the lowest the output can be is the emitter of Q1, or roughly the reference voltage) by Q3.

The in-rush current of this regulator – even with soft-start – is crazy high. To prevent the transformer from melting (or at minimum saturating), a current control is needed. This is implemented in the form of R30 and Q6. As soon as the voltage drop across R30 is higher than the threshold voltage of Q6 (~0.6V), the over-current detector engages and shuts the switching off.

R25/C3 form a delay-start mechanism. This is useful if I want to stagger the turn-on of the many regulators in the system, further limiting transient loads on the poor 20V input supply.

M4/M5/M6 and M7 form the Schmidt trigger oscillator from before, the output coupled out from the gates of M6 and M7.

Now, here’s the trick: we should only allow the transformer to be connected to the input supply, if: (a) the feedback comparator thinks the output voltage is not too high, (b) if the over-current protection is not triggered, (c) if the turn-on delay expired and (d) the oscillator is in its ‘high’ state. Essentially, we need a four-input AND gate. M8, M9, M10 and M11 (with R12 in the leading role of the common pull-up) implements this AND gate.

At this point the wave-forms are rather sloppy, so I clean the edges up with two inverters: M12 and M13 and while I’m at it, I also level-shift to the right voltage levels. Finally, M3 implements the driver for the power MOSFETS, M1 and M2. We’ve seen this part of the circuit before.

On the other side of the transformer, we see the normal forward regulator circuit: the two diodes, the LC filter (with coupled inductors to make sure we have load-independent regulation of both the positive and negative supplies) and the feedback voltage divider: R16 and R17.

With the current settings, the output voltage is a little over 16V. The current limit is set around 20A, which tells you something, I guess. True, the regulator is set up to supply 2A on each output, which (at 50% duty cycle) would translate to roughly 7-8A peak current anyway.

Colorful traces

Let’s start by looking at the output voltage (over temperature):

Right now, the soft-start and turn-on delays are set to very short time-constants; simulations already take very long as they are. In real life, they would be much longer. At any rate, you can see both of them acting on the output. Once things turn on (at around 0.25ms), the output very quickly jumps to ~6V, but then slowly reaches the plateau following the soft-start R/C time-constant. You can’t really see the temperature dependency on this curve (which is good, I guess, so let’s zoom in):

Much less nice. You see that over temperature, the voltage varies by about 800mV and the ripple in the worst case is about 200mV. This is good enough for a down-stream linear regulator, so I’m not going to quarrel with it, but it could be better for sure.

Now, let’s see the various control loops in action! The current-limiter is mostly active during the initial ramp, when the output voltage is 0:

You can see that when the input current (as measured on R30) reaches about 24A, the clamp engages. Zooming further in, you can see how the protection cuts the duty-cycle short:

This shows that the over-current control loop is quick enough to act within a single cycle of the oscillator. I think that’s good.

You can also see on the previous graph, that further bursts of operation don’t trigger the over-current detector. Let’s zoom in to one of these bursts:

Here, you see a handful of cycles of ~50% duty cycle drive pulses. This is the voltage control loop in action. At this point (due to the soft-start) it tries to regulate to around 6V output. This loop gets its feedback from after the output L/C filter and as such, it’s slow; much slower than the oscillator cycle time. This is the reason you see bursts of activity. As the reference voltage rises, the average duty cycle needs to increase and consequently the length of the bursts increase. For instance, when the reference calls for a 13V output voltage, the bursts now contain 8-9 pulses:

This bursty behavior is the cause of the output ripple as well. In effect, the outer voltage control loop has steady-state burst repeat frequency of about 30kHz, at least with this rather large load:

If I lower the load by two orders of magnitude, the cycle-time increases to the point where it too is comparable to the oscillator frequency:

You can also see how the output ripple is reduced to a mere ~2mV peak-to-peak.

Conclusion

This is a complicated circuit, no question about it. More than a dozen transistors, two transformers, lots and lots of passives. However, I think I will only need one, maybe two of these regulators in the system, so complexity matters much less here. With the fairly tight output regulation, I can minimize the voltage drop (and heat dissipation) on the down-stream linear regulators. Which is going to be the design exercise I’ll cover next.