Introduction

I promised to come back to the line drivers for core memories two chapters ago. I left you with a cliff-hanger about optimizations that can greatly reduce circuit complexity.

In this chapter, I’ll discuss these optimizations, but first, let’s start with a recap! A core memory is organized into bit-planes (or mats for some strange reason), which are a 2D matrix with horizontal and vertical wires. At the intersection of these wires, you have ferrite cores, which act as permanent magnets.

These ferrite rings can be magnetized in one of two directions, representing a binary ‘0’ or ‘1’. In order to magnetize the cores, the horizontal and vertical wires need to driven by a predetermined current level, called the half-current. These currents, when combined, induce a magnetic flip in the cores. However due to the organization of the matrix, only a single core will experience such an event if only one X and one Y line is driven by this half-current. This is the basis of how addressing in core memories work.

Reads and writes are done similarly, except with opposing current directions. A sense wire is used to read out the value from the cores and an inhibit wire is used to block a write when multiple bit-planes are combined. Many implementations combine the inhibit and sense wires into a single wire. Either way, these wires snake through every core of a bit-plane.

Reads are destructive: they return the addressed core to its ‘0’ state during the read operation. Writes (due to the fixed current directions) can only flip ‘0’-s to ‘1’-s, not the other way around. This means that every read must be followed by a write (of the old value) to restore the memory content and every write must be preceded by a read to ensure that all bits are in the ‘0’ state before the write.

That was a speed-run through core memory technology. You can find the expanded version in the chapter about core memories.

Naive addressing

Let’s look at the diagram above: you see a matrix of cores and wires running through them in the X and Y direction. This depiction is for a 64-bit memory, organized in an 8×8 matrix. We need to be able to drive a ‘half-current’ through any of the X and Y wires. At any given time up to one X and one Y line will be driven. The addressed bit is at the intersection of the enabled X and Y lines.

We also need the ability to drive this current in one direction for read and the other direction for write operations. A hugely simplified version of how driving such a line (X or Y) would work is below:

In the center you see the line with the ferrite cores stringed up on it. On the very right you see the half-current source. The rest looks exactly like an H-bridge. And that is what it is. For the rest of the discussion here though it’s better if you think of it as two half-bridges on either end of the line. The point is, that current flows through the line in one direction if Q1 and Q4 are turned on and the other direction if Q2 and Q3 are on. Any other combination will not allow current to flow. You normally don’t want to turn on Q1 and Q2 at the same time (or Q3 and Q4 for that matter) as that would simply short out the current source.

Let’s list what the control signals (A;B;C;D) should do for the various operating modes. When looking at the table below, please keep in mind that the top-side transistors are turned on by pulling their base low, while the low-side transistors are on if their bases are pulled up.

There are a few other combinations that result in no current flowing, but this is enough for now.

It’s not difficult to imagine the logic needed to generate your favorite drive signal combinations for the three states from an address bus and a couple of transaction type signals. We’ll come back to those details in a later

Of course we don’t have just one X or Y wire. We have many. In the above diagram you see eight of each. In my, much larger memory I have 128 of each.

The simplest thing to do is to simply replicate the H-bridge circuit for each X and Y line. They can potentially share the current source:

This would require (for me) 256 full bridges or 1024 transistors. Plus of course the associated decoding and control logic. It works, yes, but it’s large.

5D chess

Can we do better? Yes, indeed, we can. The realization comes from the following observation: current only flows through a particular line if the half-bridges on both ends are enabled in a coordinated way. For instance, for read operations, we can turn on the ‘C’ and ‘D’ signal high for all the lines and simply do the selection using the ‘A’ and ‘B’ controls on a per-line basis. We can do something sneakier though still: we can control the top-right and bottom-right half-bridges with the same signal and the odd-left and even-left half-bridges by another set:

This is not much of a savings just yet, but notice the potential here: we partitioned the left- and right-side drivers in such a way that there’s only one line connecting any left-side group with any right-side one. As long as we drive a single group on the left side and single group on the right, there’s going to be only one line conducting current. Exactly what we want.

Also notice another thing: since we always drive the half-bridges with the same control signals within a group, we don’t actually need individual bridges within a group: we can consolidate them into a single bridge. Now we’re cooking! But we have to be careful not to get burned… Let me draw this out before I tell you what the problem is:

In this diagram, I stopped showing how the half-bridges connect back to the current source. That’s not all that interesting anymore, you can add those connections back in your imagination.

So, the problem: the ferrite beads are stringed on long wires, so when I connect those wires together, I can’t control which one is enabled anymore. If you follow the lines you can see that in essence, I connected all lines into one loop. This is problematic as no matter which drivers I turn on, current will flow through all lines, and thus, all cores.

Before we solve this, let me redraw the diagram one last time. In this case, I will change nothing in the circuitry just move things around a little to make the next step more intuitive:

You might be questioning my sanity at this point, especially about the way the vertical lines are drawn, but trust me, there’s a method to this madness. It is very important to realize though: even though this diagram starts looking like an X/Y matrix, we’re still only talking about select lines going in one (say the X) direction. A copy of this whole thing exists for Y wires as well.

Let’s look at how the current flows through two particular wires. I’ve marked the current-flow by blue arrows in the center of the diagram. One arrow would apply to read operations, the other for writes: the currents are separated and have their wire to go through. Until we reach the first select line, that is. At this point unfortunately we tie two branches together, so the second leg of the vertical line doesn’t have separate current flows anymore. If we can fix that, we could get to a situation where current flows in one particular direction all the way to the bottom. It would also solve the problem of the big loop. To do that, let’s add some diodes to the diagram:

How do these diodes help? Remember, our problem was that we connected all select lines into a giant loop. Now, if you try to follow the same loop on whatever direction, you will find diodes that will face in the wrong direction, stymieing current flow. We are back to our old situation, where half-bridges can direct current into one particular select line and only that one.

With this trick, we’ve created from what used to be a simple line of H-bridges (essentially a 1D structure) a matrix of half-bridges with diode-pairs in the intersection points. We’ve transformed our circuit into a 2D structure. Now, I’ve said not to loose sight of the fact, that even though the topology is 2D now, we’re still dealing with just the (say) X select lines. The identical trick can be done to the Y lines as well of course. That gives us four dimensions. Also remember, that all this only works for a single bit-plane. For multi-bit memories, each bit-plane is connected in series as far as X and Y lines are concerned, but have their own sense/inhibit lines. Many memories are even physically built as a 3D cube:

After all this transformation the total dimensionality of the circuit is five. We have a 5D circuit! Pretty neat, if you ask me.

How does it scale?

My memory has 128 X and 128 Y lines. That means that this 2D re-interpretation of the select logic will have 16 horizontal half-bridges and 8 vertical ones for both X and Y. There are 128 intersection points, each having two diodes, so I will need 16*2+8*2=48 transistors and 128*2=256 diodes. Same for the Y lines. The total count now is a mere 96 transistors and 512 diodes. Quite a change from the 1024 transistors we’ve started with.

The drive logic becomes much smaller as well as the address bus needs to be broken up into four sections instead of two. The one-hot decoders become 16 or 8 output circuits instead of the 128 monsters of the previous design. All in all, this is a much cheaper circuit to build.

Outro

I have to give credit where credit is due: none of this is my idea. Let’s go back to my claim from two chapters ago. I said that not only there is this great optimization that I can do, but that I’m forced to do it. Why is that? Let’s look again at the memory module I have:

You see all those DIP chips on the side? Those are not ICs, those are diode networks. In fact, those are the 512 diodes, that I need! And since some of them were damaged, we can look at them closer too:

Cool! Anyway, I have those diodes installed already. Still, I could just remove them, right? Well, maybe, but here’s the second problem: the edge-connectors on the board connect to the “far-side” of these diode networks, essentially wiring up the whole memory into this 5D structure. There aren’t even enough pins on said connectors to get to all 256 select lines. So, if I want to use this board, I’m going to have to live with this structure and work with the diodes in place.

In return for this mental exercise, not only I get a much cheaper design, but someone already went through the trouble of soldering in the 512 diodes for me!

Of course what I described here is exactly how the PDP-11 did memory addressing as well as many many other machines of the era. It wasn’t exactly a secret, just something I didn’t know about.

This is getting long, so let me stop here. How exactly I will implement the half-bridges and the drive logic isn’t well formed in my head yet. I might opt for MOSFETs, though that’s not period-accurate. I might use BJTs, but those require a lot of extra diodes. I don’t yet know how I will build the current sources needed, how will I control current slopes and what exact timing I would want. So all those will have to stay in the shadowy recesses of the future.