Introduction

Christmas is approaching and this year Santa came early to me. I decided to splurge on a signal generator:

It’s not the cheapest on the market but not the most expensive either by any measure. Amazon has it for about $130.

It arrived, and while I’m not 100% satisfied with its performance (the rising and falling edges on its square wave could be sharper), it is good enough for the job. The job being to help me putting all my theories on these pages into practice: build some test circuits and get them through the rigor of real life.

So, in this chapter, I will go through my first few experiments and the results.

Inverter

The first thing I wanted to test is my logic ‘family’. I’m mostly interested here in how well the spice simulations match reality. To that end, I built a simple inverter:

Simple affair. I happen to have all the components in my drawer, but the BAT54 diode is only available in SMT packages. To put this together on a bread-board, I would need through hole variants. No issue, I have a different schottky diode, I can just use that. So, I built this thing… And I didn’t take any pictures, so I can’t show you how it looked. I hooked up my bench power supply, my new toy, the signal generator and a scope and turned things on.

Surprisingly everything worked the first time, I’ve seen an inverted square wave coming out on the output. Trouble was that the edges, especially the rising edge were horribly slow. The inverter could barely keep up with a 2MHz square wave. This is what it should look like:

Again, no pictures, sorry, but this is not what it looked like. More like a triangle wave with a bit of an identity crisis.

What could the problem be? Did I put the transistors in reverse? Nope. Did I get the resistor values wrong? Nope again. Is the diode in reverse? Is there a contact problem? No and no. Then, it occurred to me to look up the diode datasheet for the schottky diode I’ve used. It was a 40V/1A device, much stronger and beefier than the BAT54. Could that be the problem? Well, I don’t have the exact model in LTSpice, but there are other, similar diodes. Let’s try replacing it!

Bingo! This is what I was staring at on the scope too. So, we have the culprit, but what is the cause? After thinking about it a little, I realized this: the base of the output stage (Q25) is driven by a relatively high output impedance of about 100Ohms (R22 and R23 in parallel). So, any capacitance on that node will influence the speed of the gate. And this different, bigger diode has about 5x as stray capacitance than the BAT54. That would explain things. To verify my thought process, all I have to do is to replace the diode with the correct one. Easier said then done, as I said: the BAT54 is an SMT part. After some fumbling, I managed to solder some tiny wires on the damn thing and insert it into the circuit. And this time, I remembered to take pictures:

So, did it help? Yes, yes it did:

On this scope capture, you can see I’m measuring about 29ns rise time and 12ns fall time. The simulation would give me 20ns and 9ns respectively. So, still significantly slower, but within believable bounds. This breadboard model surely isn’t great for signal bandwidths of 17+MHz (which corresponds to a rising edge of 20ns). I will have to build a better one (full SMT on a real PCB) to get better numbers, but overall, I think I will trust the simulations. Another way of looking at things is that, in order to get the same results in simulation than I see in real life, I would need to load down the output with a 100pF capacitor. Can I believe that I have a 100pF somewhere in this crude build? Easily.

A cautionary note though: if these numbers hold up in a better quality build, it would mean that the logic has ~10ns longer propagation delay per inverter. That, in turn can easily blow my timing margins out of the water and force me to lower the clock rate from my desired 2MHz.

As far as power consumption goes, my supply reports 18mA of current draw. That’s quite in line with the simulation.

AOI gate

This is a bit harder to test, but I think it’s important. I will build up a full AIO gate. Something along these lines:

This implements OUT = ~((BIT0 & BIT1) | (BIT2 & BIT3)). What I would like to see proven is that the emitter follower input logic actually works and that its added delay is insignificant. The problem with testing is that my signal generator has only two output channels, not four. Still, I can tie the other two inputs to fixed levels and still ring the logic out.

Core memory testing

Another easy thing to try is to validate some assumptions about the core memory. I can easily build the following circuit now:

Here, I have a low-side switch that can turn some current on and off through one of the core wires. This could be the X or Y select lines or a sense/inhibit line. I can set the bench supply (V1) up such that it drives about 100mA into the load. Under normal circumstances these wires carry more like 400mA, but I want to be gentle. At least at first (not to mention that the 2N3904 can’t really carry more than 200mA). There are two points to this circuit. The first one is to measure the current shape through the core wires (R1). With some finesse I should be able to measure that as the voltage drop through R2, connected to a scope. (I would have to ground-isolate the scope, use a differential probe – which I don’t have or use math functions and two channels. I’ll have to see what works best.) Hopefully it will validate my assumption that its largely resistive in nature. Just in case though, I have D1 to absorb any EMF kick-back from the inductivity of the wire, if there’s a significant one. This can be verified by looking at the current through D1, or by looking at the shape of the turn-off voltage transient on the bottom of the load. Right now, I’m showing a 1kHz drive, but I will have to see how far can I crank it up before Q1 becomes too slow to respond. 100kHz seems doable though the recovery from saturation starts to distort the duty-cycle quite a bit.

The second thing to do is to look at what voltages these transients induce into the sense/inhibit wires. This picture shows the knitting pattern for my core memory:

It shows that the sense/inhibit lines run in parallel to the Y select lines and perpendicular with the X ones. You also see the cross-over in the middle. You have to remember though, that the sense wire snakes through the whole array, so the next pair of adjacent Y select lines have the same sense/inhibit wire going along with them. In the end, the two ends of the sense/inhibit wire is connected to the differential inputs of the sense amplifier. A single bit-plane is constructed using 128 X and 128 Y wires (a total of 16384 bits) and the sense/inhibit line goes through each X/Y intersection. Each intersection with it’s ferrite core around it forms a small transformer, creating coupling opportunities. So, if one puts a current pulse into any of the X or Y wires, one should expect 128 tiny transformers engaging and inducing some voltage into the sense/inhibit wire. True, the clever routing of the sense/inhibit wire ensures that 64 of those transformers induce voltage in the left half of the sense-inhibit wire, while the other 64 into the other. In an ideal world, these all should cancel out, at least differentially. I should expect to see large common-mode changes, but no differential voltage dropped. We don’t live in ideal world though (in case you haven’t noticed), so it will be interesting to see how much coupling there really is.

If you look at the way a sense/inhibit wire is hooked up (in the original PDP-11), you get something like this:

Now, most of this circuit is missing of course, but the top-left three resistors and three diodes (within the area marked as ‘STACK’) exists on my board as well. The resistor values are not listed here, but from the detailed schematic, it seems that the horizontal ones are 100Ohms each, while the vertical one is 500Ohms. I don’t like (or have) that -5V supply I’m supposed to connect there. For my purposes, I think I can simply ground it. It shouldn’t matter, just offsets the common mode output.

For measurement purposes, I can hook up a scope to each end of the far side of the sense/inhibit wire (or, again GND and a single channel if I ground-isolate the scope), and see what I get while I wiggle the X and Y wires.

These currents are not high enough to induce any core flips, so I won’t see any of the signal I care about, but I can get an idea of the noise, both in terms of magnitude and duration.

I built this circuit, and first drove an X wire, while measuring the feedback in one of the sense lines. Everything worked beautifully, in that I got decent (though imperfect) current ramps as measured on the sense resistor and I got nice readouts on the sense wire as well.

First, let’s look at a zoomed out waveform, showing a 100kHz drive signal:

The yellow trace measures the voltage at the top side of the sense resistor, the purple one, on the bottom side. The difference of the two is shown in white.

The blue trace is the base drive. It’s a 3.3V square wave with – as we shall see on the zoomed-in version – some ringing. This could be just a probing phenomena or real, I’m not sure.

Finally, the green trace is the voltage across the sense wire.

I probed these wires directly, that is, on the “inside” of any resistors or diodes, directly connecting to the wires in the core mesh.

The voltage supply was set to 12.78V to produce an average of 50mA current, which, at 50% duty-cycle means 100mA during the on-time.

I had a whole section on probing and trying to explain what I see on the sense/inhibit wire (the green trace). It doesn’t matter though, as it turned out this setup is extremely sensitive to probing for some reason. The only setup that really worked is if I set the scope up to do differential measurement on the two ends of the sense/inhibit wire, while not having any ground connections to anything else. That means no other probes to any other wire, no grounding the center tap of the sense wire, isolated power supply and a cut in the safety ground (not smart, but hey, YOLO).

Now, let’s zoom in! Here’s the turn-on transient:

The turn-off transient looks similar, through curiously, the current fall is not exponential as expected:

Switching to the Y wires, the picture is only slightly different:

In this next experiment, I’ve removed the protection diode from the driver circuit. This didn’t change the current ramps all that much. Yes, they got smoother, but not significantly different:

  

Concentrating on the current ramps we see the rise time is 200ns, the fall time is 236ns. Roughly the same, with and without the protection diode. Now, let’s repeat this experiment with a simple resistor as the load!

With a resistive load, we see rising edges of 150ns, and falling edges of 248ns.

If I measure the zero-current delay from the change in base-voltage, I get 500ns falling, ~50ns rising, although this one is debatable, one can make the argument for ~300ns as well. This is with the resistive load. Going back to the core stack (Y drive), we get roughly 300ns rise time (this time nice and exponential) and 500ns falling.

Overall, I think we can conclude that the X/Y loads are more or less resistive in nature and the ramp rates in my circuit are controlled by the BJT and not the load.

Flipping bits

These results really make me want to try to bit-flipping exercise as well before finalizing anything for the core memory circuit.

I decided to get a pair of H-bridges from Amazon:

They sell a pair for $7. Here’s the documentation for the board, including schematic. It is based on the L298N chip from ST. This can do 4A total (2A per channel, I guess), and is BJT based if I can believe the block diagram. That makes it a rather nice stand-in for what I will have. Seems to have current rise- and fall-times in the same general range as my simple circuit (200ns and 700ns). It has turn-on and turn-off delays much higher, than that, but I don’t think I care about that. It doesn’t have built-in protection diodes, something that the board provides though.

Each side of the bridge has different drive inputs, which I can hook up to the two channels on my signal generator. This allows me to generate a tri-state current wave-form, where I have current in either direction separated by times where no current flows.

Testing this thing is harder than it initially seemed though. I fought a lot with ground bounce and collapsing power supplies due to shoddy wiring, lots and lots of interference effects and general “real world” effects. I won’t bore you with the details.

One thing all this futzing around with differential measurements taught me is that there is rather minimal common-mode-to-differential conversion is happening inside the core mat. This is good news, though insufficient to guarantee operation: the diff amp I build will also have to maintain good common-mode rejection, which means well matched inputs. Something, I can’t even simulate.

The manual tells me that the differential signal on the amplifier input is supposed to be about 20mV from the transient-induced pulse and 40mV from a core-flip:

However, as they point it out, the transient-induced pulse height is a function of the edge rate (dI/dt), so it shouldn’t be surprising if it’s different for me.

As I explained before, probing the sense wires proved to be extremely difficult. I needed to completely isolate the scope otherwise the coupled noise would completely overwhelm my measurements. This involves an isolation transformer, a disconnected safety ground (yeah, not advised), and not connecting any grounds between the scope and the power supply or the signal generator. Not even in the mid-point of the sense/inhibit lines. This can be seen as the 60Hz hum on the common mode below.

In the following 4 scope shots the setup was the following: the X and Y wires were connected in series. There’s two ways to do this, so I tried both. I also set the drive voltage to 13 and 22V. The combined load resistance is 40Ohms, so a 22V voltage generates 550mA current through the select wires. That should be enough to cause a core flip. The 13V at the same time generates only 325mA, which is safely below the half-current, according to the documentation. Out of the four configuration, only one should cause a flip: where the X and Y currents combine constructively and are high enough. Even then, the flip should only happen when the currents are turned on, so out of the 4 transients, only on two of them. Can you see which one it is?

I can’t.

Eventually I realized that the only way to get visible core flips (or what I at the moment think are core flips) was to only use the X line to induce them. My theory is the following:

Both the X and Y wires intersect the sense/inhibit line in 64 cores, however all three intersect in only a single location (which is the point). So, if I drive the full flip current in – say – the X wire, I flip 64 cores at ones. If I drive the half current through the X and Y wires, I flip a single one. There is a 64x difference in the induced voltage in the sense-inhibit line. My probing setup is rather bad: probing the two ends of the sense/inhibit line with two probes and compute the differential voltage in the scope. The problem with that is the scale of each probe input must match the amplitude of the common-mode voltage swing, which limits the resolution on both. The difference calculation works on this resolution as well, which is simply much too coarse to show the small induced voltage from a single core flip.

I don’t think it’s a good idea to drive 1A through the very thin wires of the core mat, but with a short-enough duty cycle, it should be OK. I also limited the runs to a few seconds and let the mat to cool down in between

I also set the phase shift between the two signal generator channels to 50 degrees, which means that the current turn-on is the first of the the two close-by pulses. I ran two tests, one with a relatively low current (certainly below the flip current) and one high enough to ensure core flips. Here are the results:

I think it’s finally clear, there is a differential pulse, something that has a clear polarity flip between the two edges. So, success? Maybe?

To improve my setup, I ordered a diff amplifier as well from Amazon:

It is based on the AD8130 chip, which is a pretty sweet little thing. Almost want me to abandon my own sense-amp design and just use this. Anyway… This board will need some modifications as it has AC-coupling capacitors on both the input and the output. I’ll have to replace them with shorts, but that should be fine. I also ordered some 9V batteries and holders to give it a nice, clean, and – crucially – completely isolated power supply.

This beauty showed up today. I hooked it up, replaced the AC coupling caps with zero-ohm resistors and started taking captures.

Immediately, the quality of the traces improved by leaps and bounds. I even managed to ground the system back together – and put the drive pulses on the screen with the response without totally destroying the measurements (it’s still pretty bad, it’s just it’s not catastrophic). With this setup, I could also go back and drive both X and Y line drives and still get a decent response, meaning, I don’t have to flip 64 cores to see anything.

So, here are a couple of captures:

With 6V excitation (below half-current):

With 11V excitation (above half-current):

You can very clearly see the flip-induced pulse. The scale is a bit misleading as there is a 2x gain in the amplifier circuit. So, the peak of the pulse is at around 30mV. DEC says it should be 40mV, but I think it’s close enough. The other important metric is its position within the trace: the peak of the flip pulse is about 200ns from the end of the current ramp. I’ll give you a third shot, this time with 9V excitation. This still generates a flip, but with obviously lower amplitude:

You can see how the location of the voltage spike moved further away from the end of the current ramp, now being at about 300ns. It also reduced in amplitude to about 20mV. This is very similar to what DEC describes this pulse should be doing.

The pulse in the reverse direction is much less easy to see, mostly due to the bigger interference:

6V excitation:

11V excitation:

You can still see the pulse, but it’s pretty well buried in the noise, so picking it out with a circuit is difficult. I can just hope that the real system without a bunch of dangling wires and proper shielding will behave better. Another saving grace is that we don’t actually need to detect both kinds of pulses in real operation. One happens during reads (if we read a ‘1’), the other during writes (if we write a ‘1’). So, I can select the polarity of the pulses such that the better looking one is the one I end up using.

Conclusion

I so far haven’t encountered anything that would invalidate my assumptions. The logic gates seem solid, and the simulation results roughly match reality.

The core mat does what it should do (mostly) and I now have some concrete measurements for the shape, size and location of the flip pulse which means I can finalize the sense amp design as well as the timing circuit.

I also learned that I should expect rather large common-mode signals on the diff amp input. Several volts, potentially. I should make sure the common-mode input voltage range is sufficient and apply the proper bias, if needed to position it in the valid range for the sense amplifier. Because the common-mode input is so large, I will also have to be extra careful about common-mode rejection – something that I can’t simulate.

Finally, coupling is a b*tch. I don’t know how bad it will get in the real circuit, but judging from how much grief it caused me, I’m smelling problems.

Oh, and I should probably design a differential probe for myself with this amplifier. It is awesome!