Introduction

We are getting close to the end of discussing all the components needed for the Disintegrated machine. There are a few loose ends to tie off, a couple of which I will attack in this chapter: namely reset and clock generation.

Power good generation

To generate a reliable reset, we need to know when all the power supplies are within regulation. Ok, ok, we don’t actually have to do that. We can simply assume that after a while they settle and just delay the reset to be safe, but let’s be pedantic.

First, let’s add a power good detector to the 3.3V buck regulators:

The detection circuit is below the regulator. It contains a reference generation (Q22 and Q23), which sets the emitter voltage, and through that the threshold of the comparator (Q21). This comparator is fed from the same feedback voltage that the regulator uses, which means that you don’t have to adjust the power-good threshold and the output voltage individually: one follows the other. The output of the comparator is level-shifted and inverted (twice) to get the true output. Q18 and Q24 performs this job. The double-inversion is needed to get the polarity right, but the added extra gain to the detection logic is useful as well.

If you look back at the circuit I presented for this regulator, you might notice a few component value changes: these are needed to make the regulator work through the full -25 to 125C temperature range. With that, here are the results:

In this simulation, I purposefully overloaded the poor circuit to engage the current limiter and lower the output voltage. As you can see the power good signal dutifully changes whenever the output voltage goes out of regulation. A few things to note.

The high voltage level on the power good is determined by the pull-up resistor, which is for now connected to the 20V rail. In the real circuit, it would connect to whatever the reset generator is working from, probably one of the many 3.3V rails in the system. You see how the power-good signals polarity is actually inverted. That’s a problem and I will have to include an additional inverter stage. The idea is the following: there are many power good outputs in the system: a dozen or so 3.3V local supplies, the +/-15V and the 20V incoming rail all will have detectors on them eventually. To generate a single power-good signal from all these sources, one can connect them together into a single pull-up resistor. This implements a wired-and function, so the overall power-good signal would only go high, if all monitored supplies are judged OK. But for that to work, I need an active-high signal.

One thing, I just noticed is that the current limit is very temperature dependent: it changes by almost a factor of two. Now, this is a safety feature and should only engage under fault-condition, but with this much variability, I have doubts it can be set such that it keeps the regulator safe under all conditions. Maybe some temperature compensation is going to be needed there. I’ll contemplate that.

For the +15V and 20V rails, I’ve designed two circuits:

This variant works on the same principle as the one above (but contains the extra inverter on the output and a local reference). It’s input is the voltage source ‘B1’, which – after an emitter follower in the form of Q10 – is fed into the comparator transistor Q8. The emitter of this transistor is set to the reference voltage by Q5, which is fed through a pair of emitter followers (Q3 and Q9) from the reference voltage generated by D2. The reference is set to 3.1V through R27 and R28, but that ratio can change of course. All this emitter-follower madness is serving two purpose: first, and foremost, they provide temperature compensation by canceling out the Vbe voltage dependencies. Second, Q10 presents a very light load to the input voltage, which can be generated by by a resistor divider from whatever voltage supply we intend to monitor. The remaining three transistors, Q6, Q6 and Q4 are a series of inverters, the first is there to restore the low-level voltage to 0V and the next two to set the polarity right while having the drive transistor on the low-side (so that a common pull-up can be used).

The second variant is based on a differential amplifier:

Here, instead of emitter followers, I have a drain-follower setup in the form of M1 and M2. This lowers the input current even further. This is needed as the actual differential stage (Q1 and Q23) has relatively high input currents. The output of the differential stage is taken by a pair of inverters to get the right polarity and the right logic levels. This time, I’m using a divider in the form of R25 and R38 to bias the final output to the steepest part of the response curve to minimize temperature dependency.

The two circuits perform almost identically. They have roughly 100-120mV threshold voltage temperature dependency, they consume on the order of 5-6mA of current, they are even roughly of the same complexity: the diff-amp variant uses two fewer components than the first variant.

Here are the transfer functions:

The only notable difference is that the comparator based variant has a somewhat lower threshold voltage (due to the input emitter follower). This of course isn’t a problem, just has to be taken into account when hooking it up.

There is one important difference though: the comparator based design depends on the supply voltage quite a bit:

Since I’m not sure what supply I will use these detectors with and more importantly, I don’t want to couple supply voltage into the detector threshold, I think I will go with the diff-amp based design.

Lastly, let’s look at the -15V detector:

This is a fairly straightforward inversion of the positive variant of the design with the output stage slightly modified to get the output to the positive side of the voltage range. Due to the extra inversion inherent in the flip (negative voltages are lower than 0, so the output of the diff-amp swings ‘down’), there’s a need for an extra inverter stage on the output. I’m not going to show you graphs for the operation, you can imagine them: it is the same as the positive one, except inverted.

Reset

Now that we have all the needed power-good signals, we can construct our reset logic. This is not terribly complex of a circuit, here’s what it needs to do:

1. Combine all the power-good signals into a single wire – this is achieved by having a common pull-up resistor to the appropriate supply rail
2. Tie a reset button into the same signal, grounding it, when pressed
3. Add a delay capacitor in parallel with the reset button to cause the signal to rise slowly (but fall quickly)
4. Add a schmidt-trigger based cleanup stage to make sure noise around the threshold voltage is rejected and there are clean edges on the reset output.

We’ve seen all these building blocks before, so let’s get cranking!

In this circuit S1 is the reset switch and C1 is the delay capacitor. R16 serves as the common pull-up for all power-good detectors as well as the switch. The delay constant is set by it and C1. The schmidt trigger is created from Q1 and Q2 while Q3 and Q5 (don’t ask what happened to Q4, LTSpice is weird) shape the output signal levels and set the correct signal polarity: active low. The two threshold voltages of the schmidt trigger are set about 350mV apart (by R4) which should give us enough noise suppression with the slow rise of the RC filter.

Let’s see how it performs:

Here I’m simulating a couple of reset button pushes. You see that the falling edge of the reset output coincides with the pressing of the reset button, while the rising edge is delayed by about 50ms. This is well above the ~10ms recommended debounce time for push-buttons. This also means that the computer will be held in reset for about 50ms after all power supplies have reached their operational range, which should provide ample time for the clock circuit to stabilize. Which neatly leads me to the next topic:

Clock

A crystal oscillator is not that difficult to build, once you have an inverter. Here’s one option, courtesy of the ElecCircuit page:

My variant looks like this:

LTSpice doesn’t have a crystal model, so I put the equivalent circuit in there in the form of C10/R28/C9 and L3. You will recognize my simple inverter copied there twice. Otherwise, the circuit follows the same construct as the previous one. The simulation shows nice oscillation at 8MHz, which is the crystal frequency I modeled:

The three runs correspond to -25, 25 and 125C temperatures. So, it seems rather stable over temperature too. The startup time does vary with temperature, but is very quick still: less than 200us; well within the 50ms delay of the reset circuit.

I’ve been wondering why I don’t see the usual few-pF capacitors to ground on each end of the crystal in this circuit. I will add them in (I can always decide not to populate them in the real circuit).

The last thing to explain here is the clock frequency: I intend to run the CPU at 2MHz, so why 8MHz clock? The reason is the memory: it needs several events, timed at around 60ns apart. So I have a higher clock speed and will divide it down to eventually get the 2MHz clock. This is a bit painful as counters need D-registers, not latches. Each divide-by-two is taking a bunch of transistors. In fact, I think I will do a shift-register instead of a counter (still needs D-registers) as that setup will generate all the required clock phases without extra circuitry.

I put my oscillator together with a simple reset delay circuit and a 2-bit shift-register:

There could be some simplifications here, I might not need the two inverters in the ‘clk generation’ section, but I don’t think it matters that much: it’s 4 transistors and I pay for that only once in the whole computer.

The rest – and the reason for this being an eye-chart – is the two-bit shift register on the right. It’s built out of four D-latches, which are clocked by inverted clock phases. Overall this creates two D-registers, which are fed back such that they keep circulating the same data around, except inverted, so it takes two whole round-trips in the shift register to get back to the beginning of the cycle. The reset logic (which will derive from the true reset circuit described above eventually) is needed to set the initial condition of the register states.

Let’s see how it looks:

Nice! You see the eight phases of the generated 2MHz clock. This then can be used to generate any timing signal we need in the memory plus the clock for the processor. Furthermore the highly overlapping nature of the phases allows for glitch-free combining, very important for clocks.

Conclusion

This chapter turned out to be less painful to put together then I feared. Most circuits worked right out of the gate, or needed very little tweaking to get them there. Quite a refresher after the endless dead-ends of some of the other designs.

There are still sime I-s to dot and T-s to cross, such as some level shifters for the line drivers in the memory or the write amplifier for the cassette interface, but I think I will leave them as they are for now: unfinished. I instead will start focusing from now on on more practical matters, such as designing the individual modules in KiCAD, including their PCB layout and routing. While doing that, I will be able to re-simulate those modules in KiCADs integrated Spice environment to ensure that what I’m building matches what I doodled up in these chapters so far.

It should be exciting. I hope you will stick around to see!